How to make the avalon bus signals for the FIFO from the Quartus IP library? I selected FIFO and went through the wizard box questions so I could set up the type of FIFO I want (16 wide, 2048 deep, dual clk, etc.)

So, the after going through the FIFO setup questions, code and a .qip file was generated. I didn't see any Avalon signals in that code so I figured I need to make a wrapper for that FIFO. I wrote a wrapper with readdata, writedata, read, write, etc., but when I instantiate my FIFO module in the wrapper I get an error that says: "Instantiation error: cannot connect instance ports both by order and by name." What's this mean? Here's my code so far.

 
Top level: trying to write a wrapper for the FIFO that was created in the wizard IP catalog: 
 
module wrpFifo(
	
	input logic csi_clk,
	input logic rsi_reset, 
	input logic avs_1_read,
	input logic avs_1_write,
	output logic avs_1_readdata, 
	input logic avs_1_writedata,
	input logic avs_1_address
);
 
// For easier reading
logic clock, reset, read, write;
logic [3:0]address;
logic [15:0]readdata, writedata;
 
// Wire up Avalon bus signals
assign csi_clk = clock;		//assign is verilog.Is there a shortcut like the dot method or is that just for instantiations?
assign rsi_reset = reset;
assign avs_1_readdata = readdata;
assign avs_1_writedata = writedata;
assign avs_1_address = address;
assign avs_1_read = read;
assign avs_1_write = write;
 
// Instantiate the FIFO that was generated when I went through the 
// wizard question boxes when I chose to make a FIFO from the Quartus IP library (not using .qsys)
 
rdFifo rdFifo(
	
	.data(writedata[15:0]),
	.rdclk(clock),			//same clock for now
	.rdreq(read),
	.wrclk(clock),			//same clock for now
	.wrreq(write),
	.q(readdata[15:0]),
	.rdempty(),
	.rdfull()
);
 
endmodule
 
// The other .v file (which is within the .qip file generated) in this project is the generated FIFO which looks like this: 
 
module rdFifo(
	data,
	rdclk,
	rdreq,
	wrclk,
	wrreq,
	q,
	rdempty,
	wrfull
);
 
input [15:0]data;
input rdclk;
input rdreq;
input wrclk;
input wrclk;
 
output q;
output rdempty;
output wrfull;
 
wire [15:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
 
wire [15:0]q = sub_wire0;
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
 
// Then the generated code instantiated another FIFO based on what I chose in the Wizard questions I guess...:
 
dcfifo dcfifo_component (
	.data(data),
	.rdclk(rdclk),
	.rereq(rdreq),
	.wrclk(wrclk),
	.wrreq(wrreq),
	.q(sub_wire0),
	.rdempty(sub_wire1),
	.wrfull(sub_wire2),
	.aclr(),
	.eccstatus(),
	.rdfull(),
	.rdusedw(),
	.wrempty(),
	.wrusedw()
);
 
defparam(
	/* a bunch of settings that I chose from the wizard
	like 16-bit width, 2048 deep, etc. */
 
endmodule