Forum Discussion
TwoBit
New Contributor
New ContributorHow to make the avalon bus signals for the FIFO from the Quartus IP library? I selected FIFO and went through the wizard box questions so I could set up the type of FIFO I want (16 wide, 2048 deep, dual clk, etc.)
So, the after going through the FIFO setup questions, code and a .qip file was generated. I didn't see any Avalon signals in that code so I figured I need to make a wrapper for that FIFO. I wrote a w...
AnandRaj_S_Intel
Regular Contributor
Regular ContributorHi Rachel,
Line 49 is having an issue,
.rdfull() it should be .wrfull()
You are using by name module instantiation, using a dot(.)
.deign port name(name of wire connected to port )
Regards
Anand
