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Honored ContributorHow to make DDS with NCO megacore function?
I try to make square wave with NCO Megacore Function as below.
But, The square wave is not good for use like dds. How to make square wave like ad9850 dds ----- below is VHDL Code --------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity dds is port ( phi_inc_i : IN STD_LOGIC_VECTOR (31 DOWNTO 0); clk : IN STD_LOGIC; reset_n : IN STD_LOGIC; clken : IN STD_LOGIC; freq_mod_i : IN STD_LOGIC_VECTOR (31 DOWNTO 0); fsin_o : OUT STD_LOGIC_VECTOR (21 DOWNTO 0); out_valid : OUT STD_LOGIC; square : out std_logic ); end dds; architecture behav of dds is component nco PORT ( phi_inc_i : IN STD_LOGIC_VECTOR (31 DOWNTO 0); clk : IN STD_LOGIC; reset_n : IN STD_LOGIC; clken : IN STD_LOGIC; freq_mod_i : IN STD_LOGIC_VECTOR (31 DOWNTO 0); fsin_o : OUT STD_LOGIC_VECTOR (21 DOWNTO 0); out_valid : OUT STD_LOGIC ); end component; signal f_sin : std_logic_vector(21 downto 0); begin the_nco_is : nco port map ( phi_inc_i => phi_inc_i, clk => clk, reset_n => reset_n, clken => clken, freq_mod_i => freq_mod_i, fsin_o => f_sin, out_valid => out_valid ); fsin_o <= f_sin; the_comparator_is : process(clk, reset_n) begin if reset_n = '0' then square <= '0'; elsif rising_edge(clk) then if f_sin > "1000000000000000000000" then square <= '1'; else square <= '0'; end if; end if; end process; end behav;8 Replies
Altera_Forumwhy not just use a counter/comparator type circuit? an NCO is not a good way to generate a square in both functionality and resource usage
- Altera_Forum--- Quote Start --- But, The square wave is not good for use like dds. --- Quote End --- In which regard it's "not good"? Waste of resource can be avoided, if you design a simple fractional frequency divider, following the DDS phase accumulator principle. But it's output will be time discrete, only switching at the input clock edge. In other words, it has a jitter. If you intend an analog timing interpolation, as provided by the comparator output of the said DDS chips, you can't avoid the complete DDS effort, the sine DAC, analog filter and cocmparator.
- Altera_Forum--- Quote Start --- why not just use a counter/comparator type circuit? an NCO is not a good way to generate a square in both functionality and resource usage --- Quote End --- Is there any possible way to build the dds without nco. I just use nco for variable clock. Thanks
- Altera_Forum--- Quote Start --- In which regard it's "not good"? Waste of resource can be avoided, if you design a simple fractional frequency divider, following the DDS phase accumulator principle. But it's output will be time discrete, only switching at the input clock edge. In other words, it has a jitter. If you intend an analog timing interpolation, as provided by the comparator output of the said DDS chips, you can't avoid the complete DDS effort, the sine DAC, analog filter and cocmparator. --- Quote End --- I want to design DDS(Direct Digital Synthesizer) with nco (for variable sine wave) and comparator (for clock generation). Is this way right for variable clock generator?
- Altera_Forum
You're requirements aren't clear to me.
Do you need the sine output or only a variable clock? Do you need a low jitter, analog interpolated clock or would a fractional clock be sufficient, as generate by your above example code? In the first case, you need all the analog stuff, e.g. a DAC and a low-pass filter, and using a DDS chip means less effort. - Altera_Forum--- Quote Start --- You're requirements aren't clear to me. Do you need the sine output or only a variable clock? Do you need a low jitter, analog interpolated clock or would a fractional clock be sufficient, as generate by your above example code? In the first case, you need all the analog stuff, e.g. a DAC and a low-pass filter, and using a DDS chip means less effort. --- Quote End --- I just want to design clock generator like dds with following specs. Bandwidth : 50MHz frequency resolution : 0.5Hz Is above possible to use nco and comparator without analog stuff, e.g. a DAC, LPF and Comparator. Thanks.
- Altera_Forum
it wasn't clear that you wanted pulse and sine outputs. in this case i recommend building your own NCO so you have access to the phase accumulator output where you can more easily derive a pulse wave
- Altera_Forum
The phase accu isn't more than
Review the NCO MegaFunction manual for a detailed description.accu :unsigned (NCO_W-1 downto 0); freq :unsigned (NCO_W-1 downto 0); ... process(clk); begin if rising_edge(clk) then accu <= accu + freq; end if; end process, square <= freq(NCO_W-1);
