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In which regard it's "not good"?
Waste of resource can be avoided, if you design a simple fractional frequency divider, following the DDS phase accumulator principle. But it's output will be time discrete, only switching at the input clock edge. In other words, it has a jitter.
If you intend an analog timing interpolation, as provided by the comparator output of the said DDS chips, you can't avoid the complete DDS effort, the sine DAC, analog filter and cocmparator.
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I want to design DDS(Direct Digital Synthesizer) with nco (for variable sine wave) and comparator (for clock generation). Is this way right for variable clock generator?
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