Contributor
ContributorHi @JohnT_Intel
nConfig is an output from the CPLD and it is connected directly to the FPGA nConfig pin (input) and has a 10K pull up resistor.
It may be trying to do FPGA configuration at the start and puts nConfig line low together with Conf done (nStatus remaining high) and fails doing it (will be re-checking this) when I try to configure/program the PFL before even autodetecting the flash to program/configure it with the FPGA application code and thus when I reach that stage nConfig line is still held low !
ContributorHi @JohnT_Intel ,
Stuck with this issue and cannot find the solution.
With the combined PFL solution, PFL logic in CPLD should determine when to start Configuration process, read the data from the flash & program it and then later configure the FPGA in FPP configuration scheme.
Need correct signal control access during these stages.
conf_done, nstatus, nconfig, pfl_flash_access_granted, pfl_flash_access_request, pfl_nreset, flash_nreset
PFL combined solution documentation is NOT available. The only thing it documents is when creating 2 different PFLs, one for flash programming and one for FPGA configuration.
I'm I not right to say that conf_done should be all the time high and when Configuration kickstarts it should go low and nConfig line should be high (nStatus line high too).
nConfig stayed low?? that kept conf_done low too & tried kickstarting FPGA configuration at the end after flash programming (noticed DCLK pulsing until conf_done gone back high) and conf_done went back high at the end but the annoyed nConfig line kept being low !
ContributorHi @JohnT_Intel
Wrt your reply which I got from a different ticket :
>> Hi,
>>May I know if you are able to try to find out who is pulling the nConfig low? Is it coming from the CPLD?
>>I don't think that the PFL will pull the nConfig low without releasing it.
>>The FPGA is only using the nConfig pin as input pin and there is no way it is driving it low.
Yes, I am wondering who is pulling the nConfig pin low ?
nConfig is an output of the PFL. CPLD instantiates the PFL. It's output is directly connected to the input FPGA_nconfig pin of the FPGA and it has a pull up resistor of 10K to 3v3
Why the PFL is driving the pin low then ? It makes it look like it is held in reset state and cannot get out of that state to kickstart the FPGA configuration process at the right time
