Contributor
Regular ContributorHi,
I have concern on the nConfig and CONF_DONE pin.
The nConfig should be released except that something is driving this low. Do you have osciloscope to scope this signal?
The CONF_DONE will only be released to high by FPGA when the configuration is completed. If the nConfig is low then the CONF_DONE shouldn't be high.
ContributorHi @JohnT_Intel
Yes, I am using a logic Analyser scoping nConfig + CONF_DONE & nStatus.
Those readings I supplied were before even autodetecting the flash and loading the application code to check if FPGA is configured. You just asked me for the status of those signals after power cycle & I supplied them to you.
Why did you state that "if the nConfig is low then the CONF_DONE shouldn't be high" at that stage?
Wrt page 1:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cfg/cfg_cf51001.pdf
At the beginning before configuration starts (ref. Fig1) nConfig is low, CONF_DONE is high & nStatus is high so it looks like we are at that stage. I'm I not correct to state this ?
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I carried on autodetecting the flash & then loading the application code.
In the latest run, I noticed CONF_DONE being low, nStatus being high and nCONFIG low
Configuration somehow kickstarted because noticed DCLK pulsing and CONF_DONE went high at the end of the configuration cycle BUT nConfig was low throughout this time. Application code was not running (ie FPGA configuration not fully working).
So, yes nConfig could be the issue during the Configuration phase. Expected that pin to be high. Please confirm here.
Regards,
Kevin
ContributorHi @JohnT_Intel
After looking into the 'loader', 'Mconfig' separate PFLs within CPLD noticed at the beginning when loading / programming/configuring the 'loader' code, there is no FPGA_nconfig, FPGA_conf_done, FPGA_conf_done signals used here (note: these pins were declared later at the 'Config' PFL). Pin list of the 'loader' listed those pins as “Reserved input with a weak pull-up”. So during this stage eg pin A4 (which is used later in the 'Config' module as FPGA_nconfig) was listed for the loader as “Reserved input with a weak pull-up”, so this looks the reason why pin A4 is high at this stage (as expected due to the reserved weak pull-up resistor).
In my case with the combined PFL Loader_MConfig, pin A4 is set to FPGA_nconfig from the start BUT since there is no pull-up resistor present on the board to the FPGA_nconfig line this line cannot go high right after reset to begin the configuration cycle. And thus since FPGA_nconfig is low, the device is held in reset. Isn't this the case? Please confirm
Note:
-> FPGA_nconfig is output of the PFL module, so I do not have direct control access to this
-> nStatus & conf_done noticed pull-up resistors in place but not on the FPGA_nconfig line.
Regards,
Kevin
