Forum Discussion
Hi,
Sorry for the delay.
If you are refering to https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-gt.html, you are able to download the installation kit. Inside the installation kit, you will be able to get Max V design which contain the PFL for reference
- Knug4 years ago
Contributor
Hi @JohnT_Intel
I downloaded the kit. Thanks.
Noticed that there is a pfl_control module within MAX5. It looks pretty complicated. There are 9 instances within it. The P2 is the PFL.
Looks like the pfl_flash_access_request output of the PFL is dangling (unconnected) internally to the internal signal fl_access_req of the pfl_control module.
The control of the pfl_flash_access_granted is by the pfl_en signal which gets generated by the wdt module reset output signal. Very confused with the process inside the wdt.vhd that generates the reset_int signal (reset out).
We had a similar process within our code and I tried adding the reset_int to it within my Loader_MConfig that instantiates the PFL as follows :
process(in_clk, in_reset)
begin
if (in_reset = '0') then
r_hb_led <= '0';
r_counter <= 0;
reset_int <= '1';
elsif (rising_edge(in_clk)) then
if (r_counter = COUNTER_MAX) then
r_counter <= 0;
reset_int <= '0';
r_hb_led <= not r_hb_led;-- if(fpga_conf_done = '1') then
-- r_config_done <= '1';
-- end if;
else
r_counter <= r_counter + 1;
reset_int <= '1';
end if;
end if;
end process;
pfl_en <= reset_int;I then connected pfl_en to the pfl_flash_access_granted input pin of the PFL instance within our Loader_MConfig module.
I then generated a .pof of the Loader_MConfig module, loaded it to our programmer, program/configured it. Then Power cycled it. Autodetected the CFI flash. Loaded our application code .pof file which contains the page data info to program the flash, changed that .pof file to the flash. Then tried to Program/Configure it, BUT I get issues :
Error (209025): Can't recognize silicon ID for device 1
Error (209012): Operation failedNote: It worked just once but then when I tried to program other pages in the flash it failed with the above Error ! Looks like again it intermittently works BUT not always. I only seen it working once in 10 tries !
I powered cycled each time for a clean run BUT seen above error message.
--
I then re-run an old code with the 2 PFL's splitted and that code still works ok ie no issues with programming the flash there.
My combined to 1 PFL code what ever I do to it it does not always work ok !
- Knug4 years ago
Contributor
Hi @JohnT_Intel
Wrt the kit example I received, I went ahead this morning and added slow_clk_gen, wdt, reset_generator blocks within my PFL wrapper as was done in the MAX 5 and connected similar way to what it was doing in the kit.
Tried here to generate the pfl_nreset and pfl_flash_access_granted signals as it was done in the kit, pfl_flash_access_request output signal of the PFL was left unconnected as the kit did.
Not used the msel_reset_n process because not using AS fast or AS standard modes. Using FPP so the output of the reset_generator connects to wdt (reset_n) & reset of slow_clk_gen.
The output reset of the wdt (pfl_en) was connected to the pfl_flash_access_granted input signal of the PFL and the pfl_nreset of the PFL.
Avoided using the: reconfigure_n <= (load_image and pls_out and reset_n and srst);
as was used within the pfl_control.vhd. That has to do with reconfiguration which I have not enabled that option within my PFL, so connected the output of the reset_generator (reset) directly to the reset_n of the wdt module. Is this ok ?
Result => After programming/configuring the new generated combined PFL .pof It could not autodetect the flash and if autodetected it once it could not start erasing/programming it !
What I am doing wrong here?
Still Stuck in trying to get the combined 'Flash programming + FPGA Configuration' mode to work with 1 PFL.
- Knug4 years ago
Contributor
Q/ How do I control pfl_flash_access_granted, pfl_flash_access_request & pfl_nreset signals to achieve correct combined 1 PFL "flash programming + FPGA configuration" and without any issues when I power cycle and run it again ?
Very surprised that I cannot get a straight forward answer to this simple question !