how to generate verilog files from simulink using Altera DSP Builder

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Hello Altera guys;

I am new to altera DSP builder and I am trying to generate HDL(verilog) files using is. However, if I am not mistaken, SignalCompiler is only capable to generate VHDL files. Is their any other ways out their stating the procedures on how to generate HDL(verilog) files from simulink using Altera DSP Builder?

Kind regards

Ryan

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quote from Altera doc on dspbuilder:

DSP Builder generates VHDL and does not generate Verilog HDL. However, after youhave created a Quartus II project, you can use the quartus_map command in theQuartus II software to run a simulation netlist flow that generates files for VerilogHDL simulation.

I haven't done myself so can't answer further.

Hello Kaz;

have you tried converting VHDL to verilog? and if ever, may I know how it was done?

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Hello Kaz;

have you tried converting VHDL to verilog? and if ever, may I know how it was done?

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go to assignments/settings/EDA tool settings

choose modelsim for simulation and verilog then run compilation and you will see files.vo in modesim directory per each corner of timing.