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Altera_Forum
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10 years ago

how to generate verilog files from simulink using Altera DSP Builder

Hello Altera guys; I am new to altera DSP builder and I am trying to generate HDL(verilog) files using is. However, if I am not mistaken, SignalCompiler is only capable to generate VHDL files. ...
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Altera_Forum
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10 years ago

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Hello Kaz;

have you tried converting VHDL to verilog? and if ever, may I know how it was done?

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go to assignments/settings/EDA tool settings

choose modelsim for simulation and verilog then run compilation and you will see files.vo in modesim directory per each corner of timing.