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Honored Contributor
Honored Contributorhow to generate verilog files from simulink using Altera DSP Builder
Hello Altera guys; I am new to altera DSP builder and I am trying to generate HDL(verilog) files using is. However, if I am not mistaken, SignalCompiler is only capable to generate VHDL files. ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hello Kaz; have you tried converting VHDL to verilog? and if ever, may I know how it was done? --- Quote End --- go to assignments/settings/EDA tool settings choose modelsim for simulation and verilog then run compilation and you will see files.vo in modesim directory per each corner of timing.
