How to Connect to SOPC Avalong Bus from outside of SOPC

Hi,

I have done something like this during the last days. My solution to that problem is as follows: I created an custom Avalon component which has two slave ports, lets call them AV0 and AV1. In this custom component I instantiated the SOPC SDRAM controller. The SDRAM controller is connected with the AV0 port by an multiplexer, and the AV1 slave input serves as an control for this multiplexer. If I send a "connect" instruction to AV1, the SDRAM controller is connected to the Avalon bus of the SOPC system. If I send a "disconnect" instruction to AV1, the SDRAM controller is disconnected from the SOPC Avalon Bus and my custom logic is connected to it. In my particular application, this allows me to write the SDRAM using the NIOS processor and use my custom logic to do a very fast playback of the SDRAM data.

Hope this helps you,

Markus

This has been discussed in detail on the forum. I can't find all the posts but here are a few to try:

http://www.alteraforum.com/forum/showthread.php?t=19366&referrerid=2226

http://www.alteraforum.com/forum/showthread.php?t=12689&referrerid=2226

Jake

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Hi,

I have done something like this during the last days. My solution to that problem is as follows: I created an custom Avalon component which has two slave ports, lets call them AV0 and AV1. In this custom component I instantiated the SOPC SDRAM controller. The SDRAM controller is connected with the AV0 port by an multiplexer, and the AV1 slave input serves as an control for this multiplexer. If I send a "connect" instruction to AV1, the SDRAM controller is connected to the Avalon bus of the SOPC system. If I send a "disconnect" instruction to AV1, the SDRAM controller is disconnected from the SOPC Avalon Bus and my custom logic is connected to it. In my particular application, this allows me to write the SDRAM using the NIOS processor and use my custom logic to do a very fast playback of the SDRAM data.

Hope this helps you,

Markus

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Thanks! That does help, and can't wait to try it!

Now here's a dumb question, my system already has an altera sdram controller instantiated in sopc, so if I create a new component that has the mux and controller built in, I should remove the other one (in sopc), correct?

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Markus, I would advise to write your own Avalon master controller instead, and put it along with the SDRAM controller in your SOPC system. SOPC builder will automatically add some arbitration logic, and this solution would be easier to write, test, maintain, and re-use.

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Just curious, what does the Avalon Master Controller connected to the SDRAM controller get you? Is it easier to interface to the Avalon Master Controller from the outside (user logic) than it is to connect to the avalon bus / SDRAM controller without it?

http://www.alteraforum.com/forum/showthread.php?t=3468

http://www.altera.com/support/examples/nios2/exm-avalon-mm.html

http://www.alteraforum.com/forum/showthread.php?t=19053

http://www.alteraforum.com/forum/showthread.php?t=12689

It is easier to create a component with an Avalon master interface if you intend to share the RAM between your custom logic and other components (such as the Nios CPU). I understood from your first post that this is what you wanted to do.

SOPC builder will automatically create arbitration logic for you to share the RAM, which would be a bit more difficult to do if you had to do it yourself.

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It is easier to create a component with an Avalon master interface if you intend to share the RAM between your custom logic and other components (such as the Nios CPU). I understood from your first post that this is what you wanted to do.

SOPC builder will automatically create arbitration logic for you to share the RAM, which would be a bit more difficult to do if you had to do it yourself.

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Gotcha.. yes that's the goal.

BTW, anyone know how fast I can clock the data in from my user logic to the avalon sopc ram?

All the sopc devices ( cpu, ram, etc) are running off 100mhz.. and my user logic writes 4 bytes every 50mhz. The simple write master is configured for a 256 byte fifo. Unfortunately, when I look at the memory after a second of transfers, it looks bad. It only works when I slow the writes ***WAY**** down. I haven't played with it to see at what speed it starts to go bad, but obviously writing a single 32bit word at speeds anywhere near the avalon sopc speed doesn't work. Anyone else experience such a thing, or have an idea what's going on?

SDRAM has a high latency and many clock cycles are necessary before a word can be written or read.

You can reach Avalon speeds by using bursts, but AFAIK this is only supported by the DDR controller and not the SDR SDRAM.

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SDRAM has a high latency and many clock cycles are necessary before a word can be written or read.

You can reach Avalon speeds by using bursts, but AFAIK this is only supported by the DDR controller and not the SDR SDRAM.

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I did experiment using different memory (on chip ram, sram, sdram), but I couldn't see any difference.., the go strobe always needs to be a fraction of the avalon clock in order for it to work.