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corestar
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2 years ago

How is PCIe coreclkout_hip generated?

I'm using a Cyclone V GT PCIe Avalon ST core. It might be helpful to use coreclkout_hip to run our application layer, but it is not clear how that clock is generated and how much jitter it has. I ha...
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corestar
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2 years ago

@Wincent_Altera

Thanks for the info.

If they can really generate a stable low jitter clock inside the FPGA, it would be really useful to make that available independent of the PCIe core.

For now, I think the safest route is to just use an external clock source to drive most of the FPGA logic and coreclockout_hip for the PCIe. Lots of clock domain crossings but so be it.

Thanks,
Dave