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corestar's avatar
corestar
Icon for Contributor rankContributor
3 years ago
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How does Qsys compute BAR sizes for Avalon-MM PCIe?

I'm attempting to use the "Avalon-MM Cyclone V Hard IP for PCI Express" core. I created an example design modeled after: C:\intelFPGA_lite\19.1\ip\altera\altera_pcie\altera_pcie_cv_hip_avmm\example_...
Pcie
  • FvM's avatar
    FvM
    3 years ago
    Hi,
    BAR sizes are defined by the address map. Review chapter "Minimizing BAR Sizes and the PCIe Address Space" in Cyclone V AVMM for PCIe user manual.
corestar's avatar
corestar
Icon for Contributor rankContributor
3 years ago

Ok, I see. For my example, it automatically computed the address map based on the slaves attached to the BARs.

In the ep_g1x1.qsys example, they must have manually entered them:

The nearest power of 2 greater than 0x201000 is 22 to get the 4 MB for BAR0. Same for BAR2 with 2^15 being lowest power of 2 greater than 0x402F.

Thanks

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    Thanks FvM for helping on that, So do you still have any further question on this forum ?

    Regards,
    Wincent_Intel