How can I use Altera's HP DDR controller for fast 8x64 read?

Hi,

A newbee's question. Needs suggestion and confirmation.

I have an application in SOPC. There are 2-3 masters that need to access

a DDR SRAM. The data width for all masters are 64bits. The DDR

width is 16bits (will be 32 in the future). The controller works at half rate.

The controller is connected to DDR SRAM through Avalon MM bus in SOPC.

One of the masters needs to read 8 continuous 64 bit words at a time from

DDR. As I read Altera's HP DDR controller spec, I can only set the burst

width to 1. So, it seems that burst mode does not work.

Currently, it takes many clocks (>22) for each 64 bits reading.

It seems that I need to make the the process work in pipeline mode

in order to reduce average clock cycles needed. But how?

Do I need to create a FIFO in my application to store up to 8 reading result?

What Avalon signal should I use? readdatavalid, waitrequest)?

Any reference design?

How many clocks does full 8x64 reading process take (expected), when only this master is accessing DDR?

Thanks,

Kevin