Honored Contributori have a problem in connecting FFT IP core and the Viterbi IP core to NIOS processor as they have Avalon ST bus interfaces and the NIOS has Avalon MM interface, i dont know how can i connect those 2 types of buses together. Is there any way i can connect the FFT and the Viterbi to the NIOS processor, i will be glad if any one can help :)
Honored ContributorHi,
In SOPC Builder there are components to do this. One is the Avalon FIFO, which can be configured to have AvMM input or output and and AvST input or output. The other is the SGDMA (Scatter Gather DMA) which can be setup to have AvMM to AvST transfers, AvST to AvMM transfers, or AvMM to AvMM transfers. --dalonHonored ContributorHi
the problem is that, for the FFT or the Viterbi IP Cores when i make them inside the SOPC builder, and generate them using the Create New Component option, they have many input and output signals for handshaking (sop,eof, etc.... ) (the viterbi for example has 21 ports) and they have clock signal and reset,etc.... , the problem is that the FIFO when i use it with I/P or O/P ports as Avalon Streaming, it comes with only one port for input or output described as Avalon Streaming, how can i connect this one port with all these signals in the FFT or Viterbi ???Honored Contributor
