How Can I Connect IP Cores With Avalon-ST Bus interface to Nios Processor

Hi

the problem is that, for the FFT or the Viterbi IP Cores when i make them inside the SOPC builder, and generate them using the Create New Component option, they have many input and output signals for handshaking (sop,eof, etc.... ) (the viterbi for example has 21 ports) and they have clock signal and reset,etc.... , the problem is that the FIFO when i use it with I/P or O/P ports as Avalon Streaming, it comes with only one port for input or output described as Avalon Streaming, how can i connect this one port with all these signals in the FFT or Viterbi ???