Help with altera FFT

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I think my conclusion on your fft clk is not right. You are dividing it into 8KHz, fair enough. I wonder why not use the same 8 clk of ADC for your fft, may be it is not connected in hardware.

I am still not sure what is your ADC actual Fs. If we assume it is 8k

while your fft clk = 18750/(1152*2) = 8.138... this is a big difference

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The 8kHz signal is generated internally in the CODEC chip given the Master clock input of

18.432MHz, and I don't think this 8kHz clock is available to the outside. 18432/(1152*2) = 8. So theorectically, my FFT clock is 8kHz. However, as noted above, my actual clock input is 18.75 and not 18.432, therefore my actual FFT clock is 8.138!

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How did you do your sqrt(I^2 + Q^2)?

You can simplify it by removing sqrt if you want. Just add squred values to get power instead of amplitude.

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I am using the Altera megafunctions for doing the sqrt and square, so this is easy.

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fourth: in your fft scaling do you take account of bit-growth.

fourth: why use 29 bits for result when your data is just 16 bits, it looks excessive, you can truncate it down to 16 bits(not important now)

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According to the Altera FFT doc on the exponent scaling, 29 bits is the resulting output bit width for my FFT setup. However, I am only passing bits 19:12 to the monitor.

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As such your fft result covers 0 ~ 1 i.e starts as positive from 0 ~ .5 then negative mirror image from -.5 ~ 0

0 means 0 frequency, .5 means Fs/2 = 4KHz.

so you can label your frequency axis from 0 ~ 4 then -4 to 0

You should see two lines on either side. These two should be equal if yur input is connected to real fft only. for example if your input frequency = 2Khz

then the lines should be at +2 on your frequency axis.

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Yes, I do see the two mirror image lines on either side.

So it seems like that my problems stem from the fact that my master clock is not exactly 18.432MHz?