HDL import blocks, Simulink signal routing, and Altera port types

Hi,

This is a bit of a vague question, but maybe one of you has experienced something similar, and hopefully found the reason for it.

I have several components I have imported as HDL black boxes. All that code works, as I use it in an identical project except for Xilinx chips.

For clarity, I need to use the Simulink Goto/From routing blocks, but this seems to cause problems?? Which is wierd, because these should be absolutely transparent.

The problem I get is messages:

Error reported by S-function 'sGeneric' in 'doppler_filter_module_altera/DFM CHA/Collapse RPDS data/Delay6':

Could not infer a type for port doppler_filter_module_altera/DFM CHA/Collapse RPDS data/Delay6:input.

By pulling part of the subsystem "Collapse RPDS data" that has this Delay block in it to the next higher level subsystem - solves this particular issue, but I then get it in another place. This might simply be because the parsing order has changed, and not actually fixed anything at all.

The point is - I've been trying to chase this problem all day, and I don't know how to look for the real cause of it.

As far as I can see, everything is correctly typed, and in the correct domain (Simulink / Altera). I assume the ports of the HDL Import blocks are already typed by the VHDL inside.

I have been trying to place Tsamp rate assertions, and AltBus type assertions all over, but still does not help.

Can anyone offer any suggestions?

Kind regards,

Kevin