Contributor
Regular ContributorHi Kevin,
Yes, this configuration is tested and is working on some of our development kits as well. You may refer https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-gt.html
The design for MAX V on the dev kit can also be downloaded from the kit installation link.
For the issue that you are facing, please review the PFL IP settings once. Recommend you to do the simulations to make sure things are at least logically working,
If that goes well, then please check on following points:
1) MSEL pin settings for Cyclone V
2) Power rail, is the power reaching the specified levels for VCCPD and VCCPGM?
Regards.
ContributorHi @Ash_R_Intel
>> Does this mean 1 PFL solution will not work and requires to be split into 2 separate PFLs ?
>> Yes, this configuration is tested and is working on some of our development kits as well
Is this answer yes from you answering my above question ie "1 PFL solution will not work and requires to be split into 2 separate PFLs"? Are you answering yes to this question ?
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Seen that kit before. Commented in another ticket about it. It uses many blocks inside generating slow clock etc (looks quite complicated what they try to do there and did not pursue that route because I tried connecting things as the kit did wrt generation of granted signal, pfl_nreset etc but could still not get that to work.
I also downloaded the MAXV on the dev kit but seen as stated above many blocks within it (must be doing other things which I do not require).
Tried using the slow_clk_gen, wdt, reset_generator (generating the reset). My mode is FFP so msel chosen others in that design ie msel_reset_n = '1' that was AND'ed with the output of the wdt reset (plf_en) to connect to the pfl_nreset of the PFL.
wdt reset output was also connected to the pfl_flash_access_granted of the PFL
I did not use the 4 input AND gate to generate the reset_n (in) to the wdt. I connected directly the reset output of the reset_generator to the reset_n (in) of the wdt and the reset (in) of the slow_clk_gen
Did not use the 3 input MUX with a flop output generating the msel_reset_n. As stated I connected directly '1' to the AND gate one input. So effectively the output reset (pfl_en) of the wdt connects directly to the pfl_flash_access_granted and pfl_nreset inputs of the PFL.
Regards,
Kevin
