Contributor
Regular ContributorHi Kevin,
Does the board have proper pull-up resistors on Cyclone V device programming pins? Refer the Cyclone V Pin Connection Guidelines or even the Figures in Parallel Flash Loader Intel FPGA IP User Guide.
Are the simulations of the PFL IP working fine?
How about the timing closure?
What is the Quartus version that is being used?
There are some recommendations in the Parallel Flash Loader Intel FPGA IP User Guide, section 1.3.2, on whether to use 1 PFL or 2 PFL IPs.
Parallel Flash Loader Intel FPGA IP User Guide
Regards.
ContributorHi @Ash_R_Intel
Has anyone else tried the 1 PFL solution for programming flash + FPGA configuration, FFPx16 and manage to get it working?
Did not receive a reply on this matter.
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Yes, there are 10K pull up resistors on nStatus, conf_done and nConfig pins.
The PFL User Guide I looking all the time. It is incomplete wrt 1 PFL solution. It just describes mainly the 2 separate PFL solution.
We did not carry out any simulations on the PFL. I am looking at the validated results using a signal analyser. They were no simulations carried our before in the 2 PFL separate design too.
There are no Timinig violations seen in the design.
Using Quartus prime 20.1 Lite Edition when generating the .pof files and I was advised to use Quartus 13.1 for the programming stage. These versions of Quartus work on the 2 PFL solution.
>>There are some recommendations in the Parallel Flash Loader Intel FPGA IP User Guide, section 1.3.2, on whether to use 1 PFL or 2 PFL IPs
This is just the info listed there when it mentions 1 PFL solution :
"You can use the PFL IP core to either program the flash memory devices, configure
your FPGA, or both; however, to perform both functions, create separate PFL functions
if any of the following conditions apply to your design:
• You want to use fewer LEs.
• You modify the flash data infrequently.
• You have JTAG or In-System Programming (ISP) access to the Intel CPLD.
• You want to program the flash memory device with non-Intel FPGA data. For
example, the flash memory device contains initialization storage for an ASSP. You
can use the PFL IP core to program the flash memory device with the initialization
data and also create your own design source code to implement the read and
initialization control with the CPLD logic.
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We have JTAG access to the intel CPLD and FPGA via the USB Blaster for the purpose of programmming/configuring the PFL code, autodetecting the flash, programming the main application code via the the flash & eventually configuring the FPGA.
Does this mean 1 PFL solution will not work and requires to be split into 2 separate PFLs ?
Regards,
Kevin
