HARD IP DDR3 with UniPHY + ArriaVGX: too long not local_ready

Hello!

I am long enough work with DDR/DDR2/DDR3 IPs using Altera Device's. But this see first time.

I use 2 chips together (32 bit width) Hard IP DDR3 600 MHz. And see that during long read write transactions local_ready signal may not ready up to 1.12 us (1400 tacts of 125MHz clock). I specially at first write RAM then read using bursts and do it repeatedly (in loop). And see these holes in ready very often... I have no any timing slacks after compilation. IP was created with megawizard.

What is it? Refresh? Why is so long?

Any suggestion?

Please Help! )