ContributorI have been trying to set up the GTS PMA/FEC Direct on the Agilex 5 and would like to know how to stream parallel data to/from the GTS when the GTS does not expose a AV-Sink/Source on the parallel data interfaces?
A pic of the IP for reference:
Thanks!
Regular ContributorHi,
Just to add on, you may refer to the GTS Transceiver PHY User Guide: Agilex 5 FPGAs and SoCs -> "Table 55. Recommended Connection and Source" for further details on the coreclkin & clkout connection.
ContributorAh - thank you again! Does there also include a place to explain how to connect resets for the o_tx_clkout / o_rx_clkout components?
Regular ContributorHi,
Regarding your inquiry about the appropriate clock signals for sampling parallel data into and out of the GTS PHY, please refer to the following recommendations:
1. o_tx_clkout
Connect this clock to the component that provides data to i_tx_parallel_data. Additionally, connect o_tx_clkout to i_tx_coreclkin to ensure that both the input data and the internal parallel logic of the GTS PHY operate within the same clock domain.
2. o_rx_clkout
Connect this clock to the component responsible for sampling data from o_rx_parallel_data. Also, connect o_rx_clkout to i_rx_coreclkin to maintain clock domain consistency on the receive path.
Please let me know if you have any further questions or concerns. Thank you.
ContributorAh ok I understand now - thanks!
On the o_rx_clkout side:
It seems that the mSGDMA is required to be on the same clock domain as the component which is sampling from o_rx_parallel_data (named here as raw_to_stream) and so I have set it up as shown - will this cause issues when issuing the DMA commands from the HPS?
Regular ContributorHi,
Thank you for your question regarding streaming parallel data to/from the GTS PMA/FEC Direct PHY in Agilex 5.
As I understand it, you're working with the GTS PHY, which provides a native parallel data interface. To stream data, you’ll need to directly interface with the i_tx_parallel_data and o_rx_parallel_data buses. These are accompanied by their respective parallel clocks: i_tx_coreclkin for transmit and o_rx_clkout for receive. I believe you are using Platform Designer to instantiate this PHY IP. Please note that parallel data are conduit ports, and you’ll need to export them and connect at the top-level RTL of your design manually.
For more detailed information on how the parallel data is mapped for both TX and RX paths, I recommend referring to the GTS Transceiver PHY User Guide under the section titled “Parallel Data Mapping Information for TX and RX.”
Please let me know if you have any further questions. Thank you!
ContributorThanks @CheePin_C_Intel
This is super useful - much appreciated. Actually yes, I do have a question on both the input and output parallel data lines for the GTS:
CLOCKING:
If I wanted to feed/read the input parallel data line (i_tx_parallel_data/o_rx_parallel_data) with, for instance, some basic oscillating component (feed) or some basic sampling component (read) - what clock should I power the oscillating/sampling unit with? Should it be with the same refclock that clocks the GTS (cdr_refclk, pll_refclk, refclk_xvcr)? Or should it be with the system clock that clocks the HPS? Or something else?
BIT MAPPING:
In this configuration map, I assume that the Lower and Upper Data bits are up to the user to set - so I am wondering how to use the 79 and 38 bits?
Many thanks!
Kai
Regular ContributorHi,
Thank you for filing this case and sharing the details. I appreciate your patience. Please allow me some time to review the information, and I’ll get back to you as soon as possible.
