Hps Boot

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GTS PMA/FEC Direct set-up
I am looking through the GTS docs, and have noticed that there is a setup sequence: In the generated /hwtest directory, this is all controlled via a set of .tcl scripts through Quartus system console. My questions are 1: Where are the hex addresses defined from in the /src folder? 2: It seems this example is a standalone - excuse my ignorance, but is there a standard way to go about integrating this example into a larger project? Thanks!
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K606
4 months ago Place IP & Transceiver
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GTS PMA/FEC Direct Transceiver Streaming
I have been trying to set up the GTS PMA/FEC Direct on the Agilex 5 and would like to know how to stream parallel data to/from the GTS when the GTS does not expose a AV-Sink/Source on the parallel data interfaces? A pic of the IP for reference: Thanks!
K606
4 months ago Place IP & Transceiver
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Question about TXS interface of the PCIe IP core (AVMM) for Cyclone 10 GX
Hi Regarding the txs_address_i[w-1:0] of the TXS interface of the PCIe IP core (AVMM) for Cyclone 10 GX, the user manual states: "Address of the read or write request from the external Avalon-MM master. This address translates to 64-bit or 32-bit PCI Express addresses based on the translation table. The value is determined when the system is created." In addition, it also states: "Note: The PCI Express-to-Avalon-MM bridge supports both 32- and 64-bit addresses. If you select 64-bit addressing the bridge does not perform address translation." When I instantiate the PCIe IP core and set the Avalon-MM address width to 64-bit, the parameters "Number of address pages" and "Size of address pages" will not appear. Instead, there is "Address width of accessible PCIe memory space". The value of w in txs_address_i[w-1:0] is equal to the value of the parameter "Address width of accessible PCIe memory space". My questions are: When I choose to set the Avalon-MM address width to 64-bit, is the address on txs_address_i equal to the address of the PCIe domain to be accessed? If so, do I need to set the "Address width of accessible PCIe memory space" to 64? If I don't set it to 64, then txs_address_i cannot cover the 64-bit address. If the PCIe core does not perform address translation, how can it obtain the 64-bit PCIe domain address through this address that is less than 64 bits? In addition, it should be noted that my PCIe address is 64-bit.
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Derek_Teng
5 months ago Place IP & Transceiver
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