GTS PMA/FEC Direct set-up

I am looking through the GTS docs, and have noticed that there is a setup sequence:

In the generated /hwtest directory, this is all controlled via a set of .tcl scripts through Quartus system console.

My questions are

1: Where are the hex addresses defined from in the /src folder?

2: It seems this example is a standalone - excuse my ignorance, but is there a standard way to go about integrating this example into a larger project?

Thanks!

Hps Boot

ProFromDover_Altera
5 months ago
I'm not sure this question is posted into the proper forum, it seems more like an FPGA IP forum topic.
Where are the hex addresses defined from in the /src folder?
The example designs generated for the GTS IP generally connect one JTAG Avalon Master Bridge to the subordinate/slave interface of the IP core alone. So the address map that the system console scripts are accessing are defined by the GTS IP core itself. This is a rather complex core with multiple functions define a different base addresses within the IP core itself but you should be able to correlate the references that you see in the system-console scripts to the various register maps defined in the user guide.
Is there a standard way to go about integrating this example into a larger project?
This is a standalone design example that gets generated to evaluate the IP in this standalone configuration. There is no standard way to integrate this example into a larger project. Fundamentally, once you understand how the IP core operates in the mode that you're interested in using, you would then determine what makes sense from an implementation perspective to fit this functionality into your larger project. But since there are many different applications that the GTS can be integrated into, there is no standard way to do this. It's possible that you may find other system level example designs that would demonstrate a specific implementation of the GTS in that use case which may provide a better example of how it could be implemented in that specific use case.

6 Replies

ProFromDover_Altera
Occasional Contributor
5 months ago
I'm not sure this question is posted into the proper forum, it seems more like an FPGA IP forum topic.
Where are the hex addresses defined from in the /src folder?
The example designs generated for the GTS IP generally connect one JTAG Avalon Master Bridge to the subordinate/slave interface of the IP core alone. So the address map that the system console scripts are accessing are defined by the GTS IP core itself. This is a rather complex core with multiple functions define a different base addresses within the IP core itself but you should be able to correlate the references that you see in the system-console scripts to the various register maps defined in the user guide.
Is there a standard way to go about integrating this example into a larger project?
This is a standalone design example that gets generated to evaluate the IP in this standalone configuration. There is no standard way to integrate this example into a larger project. Fundamentally, once you understand how the IP core operates in the mode that you're interested in using, you would then determine what makes sense from an implementation perspective to fit this functionality into your larger project. But since there are many different applications that the GTS can be integrated into, there is no standard way to do this. It's possible that you may find other system level example designs that would demonstrate a specific implementation of the GTS in that use case which may provide a better example of how it could be implemented in that specific use case.
- K606
  Contributor
  5 months ago
  Thanks @ProFromDover_Altera
  Is it necessary to edit these AVMM registers in order to get a loopback running?
  Or will the default loopback setting:
  
  Suffice to get a loopback, along with this tx-rx serial setup:
  ... assign gts_i_rx_serial_data = gts_o_tx_serial_data; assign gts_i_rx_serial_data_n = gts_o_tx_serial_data_n; ... qsys_top soc_inst ( ... .intel_directphy_gts_0_o_tx_serial_data_o_tx_serial_data (gts_o_tx_serial_data), .intel_directphy_gts_0_o_tx_serial_data_n_o_tx_serial_data_n (gts_o_tx_serial_data_n), .intel_directphy_gts_0_i_rx_serial_data_i_rx_serial_data (gts_i_rx_serial_data), .intel_directphy_gts_0_i_rx_serial_data_n_i_rx_serial_data_n (gts_i_rx_serial_data_n), ... );
  Many thanks,
  K
  - ProFromDover_Altera
    Occasional Contributor
    5 months ago
    Have you looked at section 6.12 of the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs?
    It states:
    The example design runs an external loopback test by default, with the loopback_mode parameter set to 0.
    To perform an internal loopback test you must set the loopback_mode to 1 in the parameter.tcl file, located at: <design_example_dir>/hwtest/src/
    If needed, update the JTAG port ID by modifying the jtag_port_id parameter in the same file. The default value is 0.
paveetirrasrie_Altera
Frequent Contributor
4 months ago
Hello,

Good day.
I noticed you've marked Solved to the case. Kindly confirmed if the issue resolved at your end.

Regards,
Pavee
paveetirrasrie_Altera
Frequent Contributor
4 months ago
Hello,

We didn't hear from you since last update and assumed your query have been answered since you've marked as solved. Hence, the thread has been closed. If you have a new question, feel free to open a new thread to get the support from Altera experts.
Otherwise, the community users will continue to help you on this thread.

Thank you.

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GTS PMA/FEC Direct set-up

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