Contributor
Regular ContributorHi,
Regarding your inquiry about the appropriate clock signals for sampling parallel data into and out of the GTS PHY, please refer to the following recommendations:
1. o_tx_clkout
Connect this clock to the component that provides data to i_tx_parallel_data. Additionally, connect o_tx_clkout to i_tx_coreclkin to ensure that both the input data and the internal parallel logic of the GTS PHY operate within the same clock domain.
2. o_rx_clkout
Connect this clock to the component responsible for sampling data from o_rx_parallel_data. Also, connect o_rx_clkout to i_rx_coreclkin to maintain clock domain consistency on the receive path.
Please let me know if you have any further questions or concerns. Thank you.
ContributorAh ok I understand now - thanks!
On the o_rx_clkout side:
It seems that the mSGDMA is required to be on the same clock domain as the component which is sampling from o_rx_parallel_data (named here as raw_to_stream) and so I have set it up as shown - will this cause issues when issuing the DMA commands from the HPS?
