Contributor
Regular ContributorHi,
Thank you for your question regarding streaming parallel data to/from the GTS PMA/FEC Direct PHY in Agilex 5.
As I understand it, you're working with the GTS PHY, which provides a native parallel data interface. To stream data, you’ll need to directly interface with the i_tx_parallel_data and o_rx_parallel_data buses. These are accompanied by their respective parallel clocks: i_tx_coreclkin for transmit and o_rx_clkout for receive. I believe you are using Platform Designer to instantiate this PHY IP. Please note that parallel data are conduit ports, and you’ll need to export them and connect at the top-level RTL of your design manually.
For more detailed information on how the parallel data is mapped for both TX and RX paths, I recommend referring to the GTS Transceiver PHY User Guide under the section titled “Parallel Data Mapping Information for TX and RX.”
Please let me know if you have any further questions. Thank you!
ContributorThanks @CheePin_C_Intel
This is super useful - much appreciated. Actually yes, I do have a question on both the input and output parallel data lines for the GTS:
CLOCKING:
If I wanted to feed/read the input parallel data line (i_tx_parallel_data/o_rx_parallel_data) with, for instance, some basic oscillating component (feed) or some basic sampling component (read) - what clock should I power the oscillating/sampling unit with? Should it be with the same refclock that clocks the GTS (cdr_refclk, pll_refclk, refclk_xvcr)? Or should it be with the system clock that clocks the HPS? Or something else?
BIT MAPPING:
In this configuration map, I assume that the Lower and Upper Data bits are up to the user to set - so I am wondering how to use the 79 and 38 bits?
Many thanks!
Kai
