GTS DirectPHY simple simulation VHDL

Hi,
thanks for the hints.
I don't want to use the system pll clocking mode as it forces me to use elastic mode for FIFO TX PMA interface, which would cause additional datapath latency.

It seems, that a complete clean up was needed. After clean up the o_rx_ready signal was there.

If I may ask one more question.

What is the best configuration for the lowest latency in the transceiver path?
Currently I have the following:
Datapath clocking: PMA,
PMA width: 32,
TX PMA interface FIFO mode: register,
TX core interface FIFO mode: phase compensation,
tx_clkout clock source: word clock divided by 1,
RX PMA interface FIFO mode: register,
RX core interface FIFO mode: phase compensation,
rx_clkout clock source: word clock divided by 1.
No FEC,
No PCS.

Is there something I can do else to reduce the GTS transceiver latency?

Best regards.