Forum Discussion
New ContributorGTS DirectPHY simple simulation VHDL
Hi,
Few things to checkout first.
1) Are the Tx and Rx serial lines connected at the testbench? Rx lines must have data incoming on it at the configured data rate for it to lock to data and to assert rx_ready signal.
2) Check the reference clock frequency to the system pll.
3) If all the connections are correct and the input clock frequencies are also as configured in the IP, then try running it for some more time. Run upto 1ms and see.
Regards
New ContributorHi,
thanks for the hints.
I don't want to use the system pll clocking mode as it forces me to use elastic mode for FIFO TX PMA interface, which would cause additional datapath latency.
It seems, that a complete clean up was needed. After clean up the o_rx_ready signal was there.
If I may ask one more question.
What is the best configuration for the lowest latency in the transceiver path?
Currently I have the following:
Datapath clocking: PMA,
PMA width: 32,
TX PMA interface FIFO mode: register,
TX core interface FIFO mode: phase compensation,
tx_clkout clock source: word clock divided by 1,
RX PMA interface FIFO mode: register,
RX core interface FIFO mode: phase compensation,
rx_clkout clock source: word clock divided by 1.
No FEC,
No PCS.
Is there something I can do else to reduce the GTS transceiver latency?
Best regards.
Ash_R_AlteraRegular Contributor
Hi,
Glad to know that your simulation setup worked. Regarding the GTS transceiver latency, here is a general guidance:
1) Use PMA clocking mode
2) Use Register mode over other modes wherever allowed
3) Use Phase Compensation over Elastic mode of FIFO in the paths
Regards
