Forum Discussion
4 Replies
- Deshi_Intel
Regular Contributor
Hi,
We don't have the exact Ethernet 1G reference design for Stratix 10 MX dev kit board but we do have Ethernet 1G reference design for other Stratix 10 dev kit board as reference.
Triple-Speed Ethernet (TSE) IP is legacy IP we used to suppot 10M/100M/1G application that typically paired with RJ45 connector.
- I found one reference design targeting S10 GX dev kit as below
- https://fpgacloud.intel.com/devstore/platform/19.3.0/Pro/an-830-intel-fpga-triple-speed-ethernet-and-on-board-phy-chip-reference-design-for-intel-stratix-10-devices/
Likewise if your interest is more on using SFP connector then perhaps you can checkout the multirate PHY IP reference design instead of using TSE IP. This design is targeting S10 SI dev kit board
- https://fpgacloud.intel.com/devstore/platform/17.1.0/Pro/1g25g-ethernet-design-example-for-intel-stratix-10-devices/
Thanks.
Regards,
dlim
- AleCampla
New Contributor
Hi,
this actually was very useful!
Thanks a lot :)
Alessandra
- Deshi_Intel
Regular Contributor
You are welcome ! :)
- Deshi_Intel
Regular Contributor
Alright, I will be setting this case to closure.
Thanks.
Regards,
dlim