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Altera_Forum
Honored Contributor
Honored ContributorGMII <-> MII bridge in MAX II CPLD ?
Hi Folks,
In my board, I would like to use GMII to MII bridge in MAX II CPLD. But I don't have idea of > Whether it can be used in MAX II CPLD (LE utilization and device electrical characteristics support)? > If it is possible, Then any vendor can provide the ip core of this bridge ? > Do any one have design documents relating this or any suggestions from yours. Regards, Vijayan5 Replies
Altera_ForumWhat's the intended purpose of the design? GMII should be MII downward compatible by specification, normally no bridge would be necessary.
- Altera_Forum
Sorry, There is a correction. It is RGMII <-> GMII.
And in the design, CPLD should make this bridge between the processor and the switch - Altera_Forum
OK, RGMII to GMII....Please ignore this post!!!
Hi, I don't see any reason why a GMII to MII interface could not be implemeneted in a MAX II part. The CPLD should be able to be clocked fast enough (MII runs at 25MHz, GMII runs at 125MHz for Gbit ot 25Mhz for 100M) I assume you will run the GMII side at 10/100M rates to remove the need for traffic shaping/buffering in the CPLD in the GMII to MII direction) The MZX II i/o should be suitable for both MII and GMII (Spec'ed as 3.3V LVTTL if memory serves) - Altera_Forum
In terms of CPLD complexity, I expect that MAX II would be able to realize the interface. But RGMII is utilizing a DDR transmission (dual edge). MAXII unlike e.g. Cyclone FPGA has no dedicated DDR I/O circuit. So a combination of dual-edge synchronous and asynchronous logic must be used. I doubt, if the timing requirements can be met at 125 MHz with this technique.
- Altera_Forum
Thanks for all your response.
Is there any other possible solutions we have...?
