Occasional ContributorHi all,
I noticed that among the parameters of the IP library one can achieve float arithmetic with float32 and float64, but that's it, 64 seems the maximum number of bits possible. Is there another way to perhaps add/multiply/divide float128?
thanks!
Super ContributorHi,
For Intel Floating-Point IP Cores the possible maximum number of bits is 64 bits with max 11 bits for Exponent and max 52 bits for Mantissa check this document link https://www.intel.com/content/www/us/en/docs/programmable/683750/20-1/fp-functions-parameters.html
Thanks,
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Super ContributorHi,
Any further update or concern? Do you need further help on this thread?
Thanks,
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Occasional ContributorI was just trying to follow how Quartus would synthesize the following code in a function:
FUNCTION whatever (mystuff : IN float64) RETURN myvalue IS
VARIABLE val1, val2, val3 : float64;
BEGIN
val1 := mystuff + 1;
val2 := mystuff * 2
val3 := sqrt(mystuff) ;
return val1;
--return val2;
--return val3;
END whatever;
is my understanding correct that the above function won't be synthesized (as all operators +, * and sqrt require an IP) but just possibly run on the simulator? If I wanted to synthesize I would have to instantiate an IP component and use signals, is that the only way?
Super ContributorHi,
There is no problem at synthesizing the code above. You can either write your own custom code or use Intel IP. That is totally depending on you. Quartus don't have problem at synthesizing those operators.
Thanks,
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Occasional ContributorOk great,
but still on the above code, during synthesis will Quartus internally use the Altera/Intel IP (automatically)?
Related to this topic, in a vhdl architecture assuming I have float64 signals, I will be forced to instantiate IP libraries to perform floating point operations among signals, right?
Super ContributorHi,
Quartus will not automatically infer Altera/Intel IP as long as the IP is not being used. The IP core module will not be called out if IP is not used. Generally, only those logic, LUT, register, primitive, RAM or etc will be inferred based on the custom design.
Thanks,
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Occasional ContributorThanks, I am getting the picture.. sorry just one last clarification. In the function above you mentioned it can be synthesized either with "my custom code or use Intel IP", by custom code you mean an additional library I would develop or just those few lines would overload the operators +, - *, sqrt to work with floating point? If so I would guess they would consume a large number of LUTs? However it's a good news.
Would the same approach work with the following without the ALTERA floating point library?
signal trial1, trial2 : float64
begin
trial2 <= sqrt(trial2)
Super ContributorHi,
Definitely, that'll be the same approach work with the following code above without the ALTERA floating point library as long as the ALTERA library is not being used.
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
