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Altera_Forum's avatar
Altera_Forum
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17 years ago

FIR Compiler 7.2 MCV Clock to compute greater than 1

Hi all,

I've been struggling with this for a while and maybe someone can shed some light on it.

I am using the FIR Compiler 7.2 to create a FIR Filter that uses the MCV architecture with clocks to compute equal to 2. When the clocks to compute is 1, the filter works fine, when I change the clocks to compute to 2 (or above) the output of the filter goes to 0 and the ast_sink_ready also goes to 0.

I tried both methods of multicycling (i.e. by setting ast_sink_valid manually and setting it to 1 and letting the filter figure it out)

Does any one else out there have this problem?

Thanks in advance!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    I found the solution.

    It seems that since I was using a clock based off of a master clock, I needed my reset to be applied longer than I thought to clear the AST buffer.