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Altera_Forum
Honored Contributor
Honored ContributorFIR compiler & DSP blocks
This is a bit Off-topic but, When I use the FIR compiler to produce a simple FIR, single rate, 64 coeffs, 14 bit samples, 16 bit coeffs, either single channel or two channel, the compiler doesn...
Altera_ForumHonored Contributor
Honored ContributorI'm not complaining about the FIR produced. It uses few LEs and runs fast.
It is more a wonder why Altera put so much effort into including DSP blocks. Who uses them and what for? I did write my own FIR but it was hopless. The serial version had a max clk of 32MHz (in a cyclone II) and the parallel version had a max clock of 16MHz. It used a Wishbone interface. I had to convert Microchip generate coefficients from c to vhdl. Hence I upgraded to Quartus subscription.
