Forum Discussion
GPicc2
New Contributor
New Contributorfft_ii_0 is not bound
Dear Intel Community, I'm working with the FFT IP core provided by the Intel in Quartus. I've designed in vhdl a block that provides the input signal to the FFT IP core. The compilation in quartus i...
GPicc2New Contributor
New ContributorDear Vikas,
I've resolved the problem. In VHDL code generation, the Megacore Wizard provides two files: fft_core.vhd and fft_core_ii_0.sv. This files have the same ports but different inizialization values (in the latter the input ports are inizialized to 'X' while in the former the ports are inizialized to '0'). In my entity I've changed the entity fft_core with fft_core_ii_0 and the warning disappears.
Now the FFT core seems to work but I've noted that the source_sop is always set to '1' while the source_eop is alway set to '0'. From the manual these to pin must indicate the start and the end of the frame. Is it a normal behaviour? Or there is a mistake?
Thank you in advance
BR
Giovanni
