Failed to simulate DMA_Chaining example

'altpcie_hip_pipen1b' instantiates the Hard IP block for the PCIe core. It's usually located in the "pci_express_compiler-library" under your Quartus II project directory.

What version of Quartus II are you using? And is this a design from one of the Application Notes or did you create the design yourself? It sounds like the modelsim script didn't have all the files needed to be compiled.

This is the design generated when I create a pcie module from PCIe compiler wizard.

I'm using QuartusII9.1SP2

these are the library the ModelSIM searched.

C:\altera\91\modelsim_ase\altera\verilog\altera_mf

# C:\altera\91\modelsim_ase\altera\verilog\220model

# C:\altera\91\modelsim_ase\altera\verilog\sgate

# C:\altera\91\modelsim_ase\altera\verilog\altgxb

# C:\altera\91\modelsim_ase\altera\verilog\stratixiigx_hssi

# C:\altera\91\modelsim_ase\altera\verilog\stratixiv_hssi

# C:\altera\91\modelsim_ase\altera\verilog\stratixiv_pcie_hip

# C:\altera\91\modelsim_ase\altera\verilog\arriaii_hssi

# C:\altera\91\modelsim_ase\altera\verilog\arriaii_pcie_hip

# C:\altera\91\modelsim_ase\altera\verilog\cycloneiv_hssi

# C:\altera\91\modelsim_ase\altera\verilog\cycloneiv_pcie_hip

# C:\altera\91\modelsim_ase\altera\verilog\hardcopyiv_hssi

# C:\altera\91\modelsim_ase\altera\verilog\hardcopyiv_pcie_hip

# D:\Work\IPProbe\PCIe\VerisimPCIe\pcie_small_examples\chaining_dma\testbench\work

Hi Jeff,

Did you ever figure out the solution to this? I am having a very similar problem. The simulation cant find the model for the Hard PCIe IP. It lists all the simulation libraries and then says it cant find it. Which library does it live in?

Thanks,

-Greg

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Hi Jeff,

Did you ever figure out the solution to this? I am having a very similar problem. The simulation cant find the model for the Hard PCIe IP. It lists all the simulation libraries and then says it cant find it. Which library does it live in?

Thanks,

-Greg

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Hi, when creating the HardIP in megawizard, in the last step, do check the "Generate Simulation Model" ... this will generate a <name>_core.vo file. Compile this file during simulation.

Of course! Thank you. I think I was trying to use every other file except for this one.

-Greg