[Test Version][AGILEX7][QUARTUS25.3.0] - failed at elaboration process

Hello,

 

I am trying to simulate with questa fe the pcie design example (with pipe mode for external dma controller) based on agilex7 generated with quartus pro 25.3.0 but i am facing these issues when i run this script under "pcie_ed_sim_tb/pcie_ed_sim_tb/sim/mentor" as follow : vsim -do run_msim.tcl

 

# ** Warning: (vsim-3008) [CNNODP] - Component name (i_pclk__x16_l0) is not on a downward path.

 

# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589

 

# ** Error: (vsim-3043) Unresolved reference to 'i_pclk__x16_l0' in ftile_s20_v0__pcie__tile_0.z1577b.z1577b_inst.i_pclk__x16_l0.

 

# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589

 

# ** Warning: (vsim-3008) [CNNODP] - Component name (i_pclk__x4_l12) is not on a downward path.

 

# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589

 

# ** Error: (vsim-3043) Unresolved reference to 'i_pclk__x4_l12' in ftile_s20_v0__pcie__tile_0.z1577b.z1577b_inst.i_pclk__x4_l12.

 

# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589

 

# ** Warning: (vsim-3008) [CNNODP] - Component name (i_pclk__x4_l4) is not on a downward path.

 

# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589

 

# ** Error: (vsim-3043) Unresolved reference to 'i_pclk__x4_l4' in ftile_s20_v0__pcie__tile_0.z1577b.z1577b_inst.i_pclk__x4_l4.

 

# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589

 

# ** Warning: (vsim-3008) [CNNODP] - Component name (i_pclk__x8_l8) is not on a downward path.

 

# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589

 

# ** Error: (vsim-3043) Unresolved reference to 'i_pclk__x8_l8' in ftile_s20_v0__pcie__tile_0.z1577b.z1577b_inst.i_pclk__x8_l8.

 

# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589

 

# ** Warning: (vsim-3008) [CNNODP] - Component name (i_rxpipe0__dirfeedback) is not on a downward path.

 

# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589

 

# ** Error: (vsim-3043) Unresolved reference to 'i_rxpipe0__dirfeedback' in ftile_s20_v0__pcie__tile_0.z1577b.z1577b_inst.i_rxpipe0__dirfeedback.

 

# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589

 

# ** Warning: (vsim-3008) [CNNODP] - Component name (i_rxpipe0__linkevaluationfeedbackfiguremerit) is not on a downward path.

 

# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589

 

# ** Error: (vsim-3043) Unresolved reference to 'i_rxpipe0__linkevaluationfeedbackfiguremerit' in ftile_s20_v0__pcie__tile_0.z1577b.z1577b_inst.i_rxpipe0__linkevaluationfeedbackfiguremerit.

 

# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589

 

.....