Forum Discussion
Matt_P
New Contributor
New ContributorF-Tile Reference and System PLL Clocks IP
Hello FPGA Forum, I'm working with the IP "F-Tile Reference and System PLL Clocks Intel FPGA" IP and the 'Multi Channel DMA for PCI Express' example design. I'm trying to understand the connection...
yanghao1New Contributor
New ContributorHi @ventt
Is this mean that I can choose any one of refclk source in the F-tile Reference and System PLL Clocks IP, and then enable it for FGT PMA. Since this selection is logical, and I need to assign the input clk of PLL to physical pin in qsf? (Dont care about CDR feature.)
In this case, physical refclk pin is CH3, and I can select RefClk source #2 in IP GUI. Then I assign the refclk pin in qsf to CH3?
paveetirrasrie_Altera
Frequent Contributor
Frequent ContributorHi yanghao1,
The thread has been closed. Kindly post a new forum thread to get support from our experts.
Thanks
Regards,
Pavee
