F-Tile Reference and System PLL Clocks IP

Hi @ventt ,

Thanks for your reply. I've been searching through the documents provided and haven't yet cleared up my understanding.

I'm trying to understand if there's a pattern to something like the following example-
If I have a design with the 'refclk source' designated as 'refclk #3', I would expect the clock to drive the channel 3 reference pin in the F-tile, but it instead routes to the channel 2 reference pin.
Is the naming of 'refclk #3' arbitrary? Can it be renamed to 'refclk #2' to reduce confusion or mistakes?

Thank you,