F-Tile Reference and System PLL Clocks IP

Hi,

1.1. When I config System PLL IP, should I instaniate one system pll IP and enable system pll#0 and #1?

>> Given that you have two different reference clock inputs for serdes#0 and serdes#1, it's advisable to instantiate one System PLL IP block and enable both System PLL#0 and System PLL#1 within that block. This configuration allows you to generate separate clock outputs for each serdes while utilizing the same System PLL IP.

1.2. When select refclk source, can i select refclk #0 and refclk #1 seperately, then enable these two refclk for FGT PMA? or I have to select refclk #2 and #5?

>> You should select refclk #2 for serdes#0 and refclk #5 for serdes#1. Each serdes requires its own dedicated reference clock to ensure proper operation and synchronization.

1.3. What are the frequency of system pll ip output signal out_refclk_fgt_x and out_systempll_clk_x? And what's the meaning of _synthlock_x signal, indicating what clock is locked?

>>The frequency of the output signals from the System PLL IP, namely out_refclk_fgt_x and out_systempll_clk_x, would depend on the specific configuration settings you choose for the PLL. Typically, you would configure the PLL to generate output frequencies that meet the requirements of your design, such as the data rate of your serial links. The _synthlock_x signal indicates whether the PLL has locked to the input reference clock signal. When _synthlock_x is asserted, it means that the PLL has achieved phase lock with the input reference clock, ensuring stable and synchronized operation.

2. How can I connect the differential clock input to the single-ended clock input port of system pll ip?

>>You may use a Differential-to-Single-Ended Converter. You can use a dedicated IC or circuitry designed to convert a differential clock signal to a single-ended clock signal.

Best regards,

zying