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fa_fpga_enthusiast's avatar
fa_fpga_enthusiast
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Exploring why GSFI IP Core repeats sending command and address for each 4-byte data in Page Program

Dear Intel Support Team, We're working on two projects to communicate with Micron Flash Memory. The first one called the SPI project, uses the SPI 4-wire IP core and SPI driver. In the second proj...
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

I just reviewed the discussion and find it partly confusing and the reported result inconsistent.

Above, you are discussing a problem that the HAL layer is apparently unable to generate burst write access to GSFI IP, burst count always 1. Later Intel is quoting a four years old discussion stating that GSFI doesn't support page write. Reading GSFI reference about burst mode, I won't expect that the information still applies to recent GSFI IP versions, but it can be.

Did you try to verify in low level test if burst write is working approprately (translated to page write) or not?