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fa_fpga_enthusiast
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2 years ago

Exploring why GSFI IP Core repeats sending command and address for each 4-byte data in Page Program

Dear Intel Support Team, We're working on two projects to communicate with Micron Flash Memory. The first one called the SPI project, uses the SPI 4-wire IP core and SPI driver. In the second proj...
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fa_fpga_enthusiast's avatar
fa_fpga_enthusiast
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi Aik Eu,

Thank you very much for your response.

We utilize the GSFI IP Core within the platform designer, thus, the management of burst count should be handled by the Platform Designer itself (NIOS II processor and the mm_internconnet). However, based on the previous response, it seems we may need to incorporate a wrapper for the GSFI IP core to address the burst count issue. Can you please verify this interpretation?

The GSFI IP core behaves consistently for both read and write commands. Specifically, it transmits the command and address for each 4-byte read/write data. Furthermore, the burst count is determined by the length argument in the read/write commands:

  • When retrieving values from the Flash memory, we employ the intel_gsfi_read() HAL driver function, requiring the size/length of the read as an argument. Additionally, the size of the read is variable.
  • For writing values into the Flash memory, we utilize the intel_gsfi_write_block() HAL driver function. In our application, the size of writing is equal to the size of one page (256 bytes), thus, the length remains fixed in this scenario.

The management of burst count is expected to be handled by the platform designer based on the read/write length. Adding a wrapper for the burst count correction might not be a simple task.

Thank you.