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Honored Contributor
Honored ContributorError with clock connections to DDR2
This is a Cyclone IVe design, using Quartus 17.0 I have a qsys system where I have instantiated the DRAM controller "DDR2 SDRAM Controller with ALTMEMPHY" When I try to run analysis / syn...
Altera_ForumHonored Contributor
Honored ContributorHi Rod,
Here are some DDR2 example design , you can refer to the connection of these example designs and apply the same to your design. http://www.alterawiki.com/wiki/design_example_-_cyclone_iii_ddr2_sdram_altmemphy_167mhz_x32 http://www.alterawiki.com/wiki/design_example_-_stratix_iii_ddr2_sdram_uniphy_400mhz_x72 (This message was posted on behalf of Intel Corporation)
