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SERMASWATHIKA's avatar
SERMASWATHIKA
Icon for Contributor rankContributor
2 years ago

error related to ddr3 in qsys system with bdf file as top

Hi Team,

I have created on qsys design which contains NIOS II processor + ddr3 + other ips+ custom logic in cyclone v gx device.

with this I tried to compile the design in quartus 22.1 tool, i am facing 17044 error.

If the error is for Custom RTL , i can modify the io connection. But the error is throwing ddr3 ip library file connected in qsys. Even i tried one of the solution shared in intel forum that make qsys file as top file. And observed no error for qsys top file. But if i make bdf file as top, i am getting this error.

my design top file is bdf file. I cannot modify as customer recommending that. Please guide me to resolve this.

Memory

4 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hello SERMASWATHIKA,


    I would like to suggest to verify your top level design with ddr3 IP design.

    Please make sure that the port name for the ddr3 module in top level design is matching with ddr3 IP design.


    If that still cannot resolve the issue, can you provide the steps for reproducing the issue at my side?


    Regards,

    Adzim


    • SERMASWATHIKA's avatar
      SERMASWATHIKA
      Icon for Contributor rankContributor
      2 years ago

      Hi,

      Yes, I have checked the top-level design (BDF file). that is matched with ip file.

      I am using quartus 22.1.2 std version tool.

      I have implemented Nios II processor + mm bridge+ ddr3 ip + TSE ip + custom logic in qsys and generated the qsys files without any errors.

      After qsys generation, added the updated bsf file in top bdf file and started compiling the process.

      While running analysis and synthesis, 17044 error (io buffer primitive) reported for ddr3 ip library file connection.

      We even tried with soft ddr3 ip / hard ddr3 ip to reolve this issue. But for both i am getting the error.

      Please give solution to resolve this issue.

      With qsys as a top file is correct working way, how in that setup error is not showing.

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    Usually the mismatch of port name, IO, and width at RTL code is the caused of this error.

    Maybe you can try to recreate the top level design with the latest IP generated.


    Are you able to share a simple design that can reproduce the issue?

    I will help to check if the issue can be reproduce at my side.


    Regards,

    Adzim


  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.