Forum Discussion

SERMASWATHIKA's avatar
SERMASWATHIKA
Icon for Contributor rankContributor
2 years ago

error related to ddr3 in qsys system with bdf file as top

Hi Team, I have created on qsys design which contains NIOS II processor + ddr3 + other ips+ custom logic in cyclone v gx device. with this I tried to compile the design in quartus 22.1 tool, i am f...
Memory
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


Usually the mismatch of port name, IO, and width at RTL code is the caused of this error.

Maybe you can try to recreate the top level design with the latest IP generated.


Are you able to share a simple design that can reproduce the issue?

I will help to check if the issue can be reproduce at my side.


Regards,

Adzim