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JMa5's avatar
JMa5
Icon for New Contributor rankNew Contributor
7 years ago

Error Loading Design when open FFT IP core in Modelsim

Hi all,

My FFT design have a calculation length of 1024 with 16 bit wide. I set up my FFT to be streaming mode, and everything passed compilation. However, when I opened modelsim to view the result. It give me an error message: "Error: (vsim-3033) C:/Users/majin/Desktop/projects/fft_core_trial/fft_1024/synthesis/submodules/fft_1024_fft_ii_0.sv(59): Instantiation of 'asj_fft_sglstream' failed. The design unit was not found."

Does anyone have any idea about this? I am looking forward to your posts. Thank you very much!

3 Replies

  • Vicky1's avatar
    Vicky1
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    This error occurs when missing any library or missing some instance used in design.

    1. Can you please check the 'sj_fft_sglstream' design unit is available under the top model?

    2. Can you provide your project file?(.qpf file or Go to "Project->Archive Project..")

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards

    Vikas Jathar

    (This message was posted on behalf of Intel Corporation)

  • JMa5's avatar
    JMa5
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hi,

    The "asj_fft_sglstream" design unit is available. That is why I am confusing about this. I have attach my project file. Thank you very much for your help!

  • Vicky1's avatar
    Vicky1
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    In order to load and simulate the design successfully the following files need to be compiled in order :

    1. From the fft_1024/simulation folder - fft_024.v

    2. From the fft_1024/simulation/submodules folder –

    a. All of the _pkg.vhd files first

    b. Then the _roundsat.vhd file

    c. Followed by the rest of the .vhd files

    3. Next, compile the files in the fft_1024/simulation/submodules/mentor folder-

    a. The Verilog files (there are only 2 of them)

    b. All of the pkg files first

    c. Then the apn_* VHDL files

    d. Followed by the asj_* VHDL files -> except the asj_fft_sglstream. This one needs to be compiled last.

    e. Next compile the rest of the files auk_* VHDL

    f. Lastly compile the asj_fft_sglstream.vhd file.

    4. All of the files should be compiled successfully and you should be able to see them in the work folder.

    5. Now simulate the fft_1024_wrapper module. It will load successfully.

    Best Regards

    Vikas Jathar

    (This message was posted on behalf of Intel Corporation)