Error Loading Design when open FFT IP core in Modelsim

Hi,

In order to load and simulate the design successfully the following files need to be compiled in order :

1. From the fft_1024/simulation folder - fft_024.v

2. From the fft_1024/simulation/submodules folder –

a. All of the _pkg.vhd files first

b. Then the _roundsat.vhd file

c. Followed by the rest of the .vhd files

3. Next, compile the files in the fft_1024/simulation/submodules/mentor folder-

a. The Verilog files (there are only 2 of them)

b. All of the pkg files first

c. Then the apn_* VHDL files

d. Followed by the asj_* VHDL files -> except the asj_fft_sglstream. This one needs to be compiled last.

e. Next compile the rest of the files auk_* VHDL

f. Lastly compile the asj_fft_sglstream.vhd file.

4. All of the files should be compiled successfully and you should be able to see them in the work folder.

5. Now simulate the fft_1024_wrapper module. It will load successfully.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)