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{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.0.0 Build 595 04/25/2017 SJ Standard Edition " "Version 17.0.0 Build 595 04/25/2017 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1533689955507 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 08 08:59:15 2018 " "Processing started: Wed Aug 08 08:59:15 2018" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1533689955507 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1533689955507 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off fft_1024 -c fft_1024 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off fft_1024 -c fft_1024" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1533689955508 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1533689957109 ""}
{ "Warning" "WVLGO_INVALID_TIMESCALE_SELECTED_FOR_PLL_DESIGN" "" "An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool." {  } {  } 0 202000 "An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool." 0 0 "EDA Netlist Writer" 0 -1 1533689959732 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "fft_1024_8_1200mv_85c_slow.vo C:/Users/majin/Desktop/projects/fft_core_trial/simulation/modelsim/ simulation " "Generated file fft_1024_8_1200mv_85c_slow.vo in folder \"C:/Users/majin/Desktop/projects/fft_core_trial/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1533689959742 ""}
{ "Warning" "WVLGO_INVALID_TIMESCALE_SELECTED_FOR_PLL_DESIGN" "" "An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool." {  } {  } 0 202000 "An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool." 0 0 "EDA Netlist Writer" 0 -1 1533689960030 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "fft_1024_8_1200mv_0c_slow.vo C:/Users/majin/Desktop/projects/fft_core_trial/simulation/modelsim/ simulation " "Generated file fft_1024_8_1200mv_0c_slow.vo in folder \"C:/Users/majin/Desktop/projects/fft_core_trial/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1533689960035 ""}
{ "Warning" "WVLGO_INVALID_TIMESCALE_SELECTED_FOR_PLL_DESIGN" "" "An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool." {  } {  } 0 202000 "An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool." 0 0 "EDA Netlist Writer" 0 -1 1533689960332 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "fft_1024_min_1200mv_0c_fast.vo C:/Users/majin/Desktop/projects/fft_core_trial/simulation/modelsim/ simulation " "Generated file fft_1024_min_1200mv_0c_fast.vo in folder \"C:/Users/majin/Desktop/projects/fft_core_trial/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1533689960336 ""}
{ "Warning" "WVLGO_INVALID_TIMESCALE_SELECTED_FOR_PLL_DESIGN" "" "An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool." {  } {  } 0 202000 "An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool." 0 0 "EDA Netlist Writer" 0 -1 1533689960677 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "fft_1024.vo C:/Users/majin/Desktop/projects/fft_core_trial/simulation/modelsim/ simulation " "Generated file fft_1024.vo in folder \"C:/Users/majin/Desktop/projects/fft_core_trial/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1533689960683 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "fft_1024_8_1200mv_85c_v_slow.sdo C:/Users/majin/Desktop/projects/fft_core_trial/simulation/modelsim/ simulation " "Generated file fft_1024_8_1200mv_85c_v_slow.sdo in folder \"C:/Users/majin/Desktop/projects/fft_core_trial/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1533689960742 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "fft_1024_8_1200mv_0c_v_slow.sdo C:/Users/majin/Desktop/projects/fft_core_trial/simulation/modelsim/ simulation " "Generated file fft_1024_8_1200mv_0c_v_slow.sdo in folder \"C:/Users/majin/Desktop/projects/fft_core_trial/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1533689960781 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "fft_1024_min_1200mv_0c_v_fast.sdo C:/Users/majin/Desktop/projects/fft_core_trial/simulation/modelsim/ simulation " "Generated file fft_1024_min_1200mv_0c_v_fast.sdo in folder \"C:/Users/majin/Desktop/projects/fft_core_trial/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1533689960823 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "fft_1024_v.sdo C:/Users/majin/Desktop/projects/fft_core_trial/simulation/modelsim/ simulation " "Generated file fft_1024_v.sdo in folder \"C:/Users/majin/Desktop/projects/fft_core_trial/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1533689960860 ""}
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