--scfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" ALMOST_EMPTY_VALUE=1 ALMOST_FULL_VALUE=5 DEVICE_FAMILY="Cyclone IV E" ENABLE_ECC="FALSE" LPM_NUMWORDS=7 LPM_SHOWAHEAD="OFF" LPM_WIDTH=38 LPM_WIDTHU=3 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="OFF" RAM_BLOCK_TYPE="AUTO" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr almost_full clock data empty q rdreq sclr(gnd) usedw wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Stratix II" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=Auto"
--VERSION_BEGIN 17.0 cbx_altdpram 2017:04:25:18:06:29:SJ cbx_altera_counter 2017:04:25:18:06:29:SJ cbx_altera_syncram 2017:04:25:18:06:29:SJ cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_fifo_common 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_counter 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_scfifo 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ  VERSION_END


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FUNCTION a_dpfifo_jc81 (aclr, clock, data[37..0], rreq, sclr, wreq)
RETURNS ( empty, q[37..0], usedw[2..0]);

--synthesis_resources = lut 8 M9K 2 reg 18 
SUBDESIGN scfifo_v2j1
( 
	aclr	:	input;
	almost_full	:	output;
	clock	:	input;
	data[37..0]	:	input;
	empty	:	output;
	q[37..0]	:	output;
	rdreq	:	input;
	sclr	:	input;
	usedw[2..0]	:	output;
	wrreq	:	input;
) 
VARIABLE 
	dpfifo : a_dpfifo_jc81;
	dffe_af : dffe;
	comparison_af0	: WIRE;
	comparison_af1	: WIRE;
	comparison_af2	: WIRE;
	comparison_pre_af0	: WIRE;
	comparison_pre_af1	: WIRE;
	comparison_pre_af2	: WIRE;
	const_node_sclr	: NODE;
	wire_af[2..0]	: WIRE;
	wire_pre_af[2..0]	: WIRE;

BEGIN 
	dpfifo.aclr = aclr;
	dpfifo.clock = clock;
	dpfifo.data[] = data[];
	dpfifo.rreq = rdreq;
	dpfifo.sclr = sclr;
	dpfifo.wreq = wrreq;
	dffe_af.clk = clock;
	dffe_af.clrn = (! aclr);
	dffe_af.d = ((dffe_af.q & (dffe_af.q $ (sclr # ((comparison_af2 & (! wrreq)) & rdreq)))) # ((! dffe_af.q) & ((((! sclr) & comparison_pre_af2) & wrreq) & (! rdreq))));
	almost_full = dffe_af.q;
	comparison_af0 = (dpfifo.usedw[0..0] $ wire_af[0..0]);
	comparison_af1 = ((dpfifo.usedw[1..1] $ wire_af[1..1]) & comparison_af0);
	comparison_af2 = ((dpfifo.usedw[2..2] $ wire_af[2..2]) & comparison_af1);
	comparison_pre_af0 = (dpfifo.usedw[0..0] $ wire_pre_af[0..0]);
	comparison_pre_af1 = ((dpfifo.usedw[1..1] $ wire_pre_af[1..1]) & comparison_pre_af0);
	comparison_pre_af2 = ((dpfifo.usedw[2..2] $ wire_pre_af[2..2]) & comparison_pre_af1);
	empty = dpfifo.empty;
	q[] = dpfifo.q[];
	const_node_sclr = sclr;
	usedw[] = dpfifo.usedw[];
	wire_af[] = ( B"0", B"1", B"0");
	wire_pre_af[] = ( B"0", B"1", B"1");
END;
--VALID FILE
