--a_dpfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone IV E" ENABLE_ECC="FALSE" LPM_NUMWORDS=7 LPM_SHOWAHEAD="OFF" lpm_width=34 lpm_widthu=3 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" aclr clock data empty q rreq sclr usedw wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Stratix II" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=Auto"
--VERSION_BEGIN 17.0 cbx_altdpram 2017:04:25:18:06:29:SJ cbx_altera_counter 2017:04:25:18:06:29:SJ cbx_altera_syncram 2017:04:25:18:06:29:SJ cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_fifo_common 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_counter 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_scfifo 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ  VERSION_END


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FUNCTION altsyncram_m8j1 (address_a[2..0], address_b[2..0], clock0, clock1, clocken1, data_a[33..0], wren_a)
RETURNS ( q_b[33..0]);
FUNCTION cmpr_gs8 (dataa[2..0], datab[2..0])
RETURNS ( aeb);
FUNCTION cntr_tnb (aclr, clock, cnt_en, sclr)
RETURNS ( q[1..0]);
FUNCTION cntr_ao7 (aclr, clock, cnt_en, sclr, updown)
RETURNS ( q[2..0]);
FUNCTION cntr_unb (aclr, clock, cnt_en, sclr)
RETURNS ( q[2..0]);

--synthesis_resources = M9K 1 reg 9 
SUBDESIGN a_dpfifo_fc81
( 
	aclr	:	input;
	clock	:	input;
	data[33..0]	:	input;
	empty	:	output;
	q[33..0]	:	output;
	rreq	:	input;
	sclr	:	input;
	usedw[2..0]	:	output;
	wreq	:	input;
) 
VARIABLE 
	FIFOram : altsyncram_m8j1;
	empty_dff : dffe;
	full_dff : dffe;
	low_addressa[2..0] : dffe;
	rd_ptr_lsb : dffe;
	usedw_is_0_dff : dffe;
	usedw_is_1_dff : dffe;
	wrreq_delay : dffe;
	almost_full_comparer : cmpr_gs8;
	two_comparison : cmpr_gs8;
	rd_ptr_msb : cntr_tnb;
	usedw_counter : cntr_ao7;
	wr_ptr : cntr_unb;
	asynch_read_counter_enable	: WIRE;
	empty_out	: WIRE;
	pulse_ram_output	: WIRE;
	ram_read_address[2..0]	: WIRE;
	rd_ptr[2..0]	: WIRE;
	usedw_is_0	: WIRE;
	usedw_is_1	: WIRE;
	usedw_is_2	: WIRE;
	usedw_will_be_0	: WIRE;
	usedw_will_be_1	: WIRE;
	valid_rreq	: WIRE;
	valid_wreq	: WIRE;
	wait_state	: WIRE;

BEGIN 
	FIFOram.address_a[] = wr_ptr.q[];
	FIFOram.address_b[] = ram_read_address[];
	FIFOram.clock0 = clock;
	FIFOram.clock1 = clock;
	FIFOram.clocken1 = pulse_ram_output;
	FIFOram.data_a[] = data[];
	FIFOram.wren_a = valid_wreq;
	empty_dff.clk = clock;
	empty_dff.clrn = (! aclr);
	empty_dff.d = ((! (usedw_will_be_0 # wait_state)) & (! sclr));
	full_dff.clk = clock;
	full_dff.clrn = (! aclr);
	full_dff.d = ((! sclr) & (((valid_wreq & (! valid_rreq)) & almost_full_comparer.aeb) # (full_dff.q & (! (valid_wreq $ valid_rreq)))));
	low_addressa[].clk = clock;
	low_addressa[].clrn = (! aclr);
	low_addressa[].d = ((! sclr) & ((asynch_read_counter_enable & rd_ptr[]) # ((! asynch_read_counter_enable) & low_addressa[].q)));
	rd_ptr_lsb.clk = clock;
	rd_ptr_lsb.clrn = (! aclr);
	rd_ptr_lsb.d = ((! rd_ptr_lsb.q) & (! sclr));
	rd_ptr_lsb.ena = (asynch_read_counter_enable # sclr);
	usedw_is_0_dff.clk = clock;
	usedw_is_0_dff.clrn = (! aclr);
	usedw_is_0_dff.d = (! usedw_will_be_0);
	usedw_is_1_dff.clk = clock;
	usedw_is_1_dff.clrn = (! aclr);
	usedw_is_1_dff.d = usedw_will_be_1;
	wrreq_delay.clk = clock;
	wrreq_delay.clrn = (! aclr);
	wrreq_delay.d = ((! sclr) & valid_wreq);
	almost_full_comparer.dataa[] = B"110";
	almost_full_comparer.datab[] = usedw_counter.q[];
	two_comparison.dataa[] = usedw_counter.q[];
	two_comparison.datab[] = ( B"0", B"1", B"0");
	rd_ptr_msb.aclr = aclr;
	rd_ptr_msb.clock = clock;
	rd_ptr_msb.cnt_en = (asynch_read_counter_enable & (! rd_ptr_lsb.q));
	rd_ptr_msb.sclr = sclr;
	usedw_counter.aclr = aclr;
	usedw_counter.clock = clock;
	usedw_counter.cnt_en = (valid_wreq $ valid_rreq);
	usedw_counter.sclr = sclr;
	usedw_counter.updown = valid_wreq;
	wr_ptr.aclr = aclr;
	wr_ptr.clock = clock;
	wr_ptr.cnt_en = valid_wreq;
	wr_ptr.sclr = sclr;
	asynch_read_counter_enable = pulse_ram_output;
	empty = empty_out;
	empty_out = (! empty_dff.q);
	pulse_ram_output = valid_rreq;
	q[] = FIFOram.q_b[];
	ram_read_address[] = (((! asynch_read_counter_enable) & low_addressa[].q) # (asynch_read_counter_enable & rd_ptr[]));
	rd_ptr[] = ( rd_ptr_msb.q[], (! rd_ptr_lsb.q));
	usedw[] = usedw_counter.q[];
	usedw_is_0 = (! usedw_is_0_dff.q);
	usedw_is_1 = usedw_is_1_dff.q;
	usedw_is_2 = two_comparison.aeb;
	usedw_will_be_0 = (! ((! sclr) & (! (((usedw_is_1 & valid_rreq) & (! valid_wreq)) # (usedw_is_0 & (! (valid_wreq $ valid_rreq)))))));
	usedw_will_be_1 = ((! sclr) & ((((usedw_is_2 & (! valid_wreq)) & valid_rreq) # (usedw_is_1 & (! (valid_wreq $ valid_rreq)))) # ((usedw_is_0 & valid_wreq) & (! valid_rreq))));
	valid_rreq = rreq;
	valid_wreq = wreq;
	wait_state = (usedw_will_be_1 & valid_wreq);
END;
--VALID FILE
