--dffpipe CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DELAY=0 WIDTH=36 d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 17.0 cbx_mgl 2017:04:25:18:09:28:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ  VERSION_END


-- Copyright (C) 2017  Intel Corporation. All rights reserved.
--  Your use of Intel Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Intel Program License 
--  Subscription Agreement, the Intel Quartus Prime License Agreement,
--  the Intel MegaCore Function License Agreement, or other 
--  applicable license agreement, including, without limitation, 
--  that your use is for the sole purpose of programming logic 
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--  agreement for further details.



--synthesis_resources = 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";

SUBDESIGN dffpipe_d3c
( 
	d[35..0]	:	input;
	q[35..0]	:	output;
) 

BEGIN 
	q[] = d[];
END;
--VALID FILE
