ContributorEMIF simulation protocol and result
Dear Support,
I am running EMIP example simulation, using platform designer generate an example with presets ( Arria 10 GX FPGA Development Kit with DDR4 HILO) , it runs till the transcript console claim the simulation passed. it is pretty exciting result.
# AbPHY [5167220000]: RD data=8e0000e41e0073ab00 @ 004e26027e (GBRC=0/0/02713/00278)
# AbPHY [5167220000]: RD data=3e5000004c2500007c @ 004e26027f (GBRC=0/0/02713/00278)
# --- SIMULATION PASSED ---
# ** Note: $finish : ../../ip/ed_sim/ed_sim_sim_checker/altera_emif_sim_checker_191/sim/altera_emif_sim_checker.sv(243)
# Time: 516870852 ps Iteration: 0 Instance: /ed_sim/sim_checker/sim_checker
I expect that the memory interface to DDR module has some signals toggling. but I couldn't see it.
all signals on the memory interface are all XXXXXXXXXXXXXXXXXXXXXXXXXXXX.
Is there a document describe the protocol of the example simulation? what it is doing? what is the input to the EMIF module, and what is the export to the DDR module?
As a learner, the detail is much more important than the “Simulation Passed” result。 how can I see the signals on the DDR bus?
looking forward to hear from you.
David
Hello David,
I think that you have applied the Abstract PHY mode in the EMIF IP parameter editor.
This is an expected behavior during the simulation.
You can visit the link below that explain the Abstract PHY mode.
You can change the calibration mode to Full Calibration to analyze the full calibration flow.
But by enabling the Full Calibration mode, the simulation will run longer than the Abstract PHY mode.
I don't think that there is any documentation that describes the example design simulation.
You can take a look in the link below for the DDR calibration flow.
https://www.systemverilog.io/ddr4-initialization-and-calibration
I hope that can help you.
Regards,
Adzim
