Forum Discussion
ContributorEMIF simulation protocol and result
Hello David,
I think that you have applied the Abstract PHY mode in the EMIF IP parameter editor.
This is an expected behavior during the simulation.
You can visit the link below that explain the Abstract PHY mode.
You can change the calibration mode to Full Calibration to analyze the full calibration flow.
But by enabling the Full Calibration mode, the simulation will run longer than the Abstract PHY mode.
I don't think that there is any documentation that describes the example design simulation.
You can take a look in the link below for the DDR calibration flow.
https://www.systemverilog.io/ddr4-initialization-and-calibration
I hope that can help you.
Regards,
Adzim
Regular ContributorHello David,
I think that you have applied the Abstract PHY mode in the EMIF IP parameter editor.
This is an expected behavior during the simulation.
You can visit the link below that explain the Abstract PHY mode.
You can change the calibration mode to Full Calibration to analyze the full calibration flow.
But by enabling the Full Calibration mode, the simulation will run longer than the Abstract PHY mode.
I don't think that there is any documentation that describes the example design simulation.
You can take a look in the link below for the DDR calibration flow.
https://www.systemverilog.io/ddr4-initialization-and-calibration
I hope that can help you.
Regards,
Adzim
ContributorHi Adzim
Nice to hear from you again. thank you very much, I intentionally enabled abstract PHY mode to expedite the simulation, but I don't really understand what it means. if I understand correctly now. I write to an address, for example 0x2000, a value 0xaaaa, even it didn't forward to the external memory module, when I read to the same address, I will read this 0xaaaa back. right? abstract PHY is a little abstract.
Best Regards,
David
