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dsun01's avatar
dsun01
Icon for Contributor rankContributor
3 years ago
Solved

EMIF simulation protocol and result

Dear Support, I am running EMIP example simulation, using platform designer generate an example with presets ( Arria 10 GX FPGA Development Kit with DDR4 HILO) , it runs till the transcript consol...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello David,


I think that you have applied the Abstract PHY mode in the EMIF IP parameter editor.

This is an expected behavior during the simulation.

You can visit the link below that explain the Abstract PHY mode.

https://www.intel.com/content/www/us/en/docs/programmable/683106/21-1-19-2-0/abstract-phy-simulation.html


You can change the calibration mode to Full Calibration to analyze the full calibration flow.

But by enabling the Full Calibration mode, the simulation will run longer than the Abstract PHY mode.


I don't think that there is any documentation that describes the example design simulation.

You can take a look in the link below for the DDR calibration flow.

https://www.systemverilog.io/ddr4-initialization-and-calibration

I hope that can help you.


Regards,

Adzim


  • dsun01's avatar
    dsun01
    Icon for Contributor rankContributor
    3 years ago

    Hi Adzim

    Nice to hear from you again. thank you very much, I intentionally enabled abstract PHY mode to expedite the simulation, but I don't really understand what it means. if I understand correctly now. I write to an address, for example 0x2000, a value 0xaaaa, even it didn't forward to the external memory module, when I read to the same address, I will read this 0xaaaa back. right? abstract PHY is a little abstract.

    Best Regards,

    David