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Altera_Forum's avatar
Altera_Forum
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9 years ago

EMIF core clock sharing problem

Hi, I'm trying to connect two EMIF QDRII controlers with shared clock on arria 10 (hard PHY and Soft Controller). I had generated EMIF slave component and connected it "clks_sharing_slave_in" t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

In the newer QII version like 17.0. Once you turn on the core clock option, it will disable the pll_ref_clk pin for slave component. This mean the pll_ref_clk also will connect internally through the mater-slave connection. So, you will not see this type of conflict anymore.

(This message was posted on behalf of Intel Corporation)