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mel_tong's avatar
mel_tong
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12 months ago

E-Tile Transceiver PHY Agilex data rate is 10G, but hssi_ehip_lane_ehip_rate is rate_25gx1

Hello,I configured the E-Tile Transceiver PHY Agilex7 IP ; and the Transceiver configuration rules is Gearbox 64/66 ;mode is TX/RX Duplex. TX and RX PMA data rate is 10312.5Mhz; PMA reference clock freq is 156.25Mhz. but generate the HDL ,the .v hssi_ehip_lane_ehip_rate parameter is "rate_25gx1",not "rate_10gx1". When connecting to a 10g network, the receiver of the other party cann't receive right data.

Ethernet

16 Replies

  • WeiHanT_Intel's avatar
    WeiHanT_Intel
    Icon for Moderator rankModerator
    11 months ago

    Thank you for reaching out to Altera Community Forum. Please be informed that the SME in this area is currently Out of Office. Expected to resume work on 30-Dec'24. We apologize for any delay in response and appreciate your patience and understanding.

    Kind regards,


    • mel_tong's avatar
      mel_tong
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      10 months ago

      hi,

      Could you help me for my question?

      Thank you very much,

  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    10 months ago

    Hello Mel_tong,


    Apologized for the delayed response.

    May I know what's the protocol set in Eth Hard IP? Is it 10G/25G?


    Regards,

    Pavee


  • mel_tong's avatar
    mel_tong
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    10 months ago

    Hi Pavee,

    I not used E-Tile Ethernet hard ip, I use E-Tile Transceiver PHY IP.

    And the parameter settings for this IP core are as follows:

    Transceiver configuration rules select: Gearbox 64/66

    Transceiver mode : TX/RX duplex

    Number of data channels is 1

    TX/RX PMA modulation type is NRZ

    data rate 10312.5Mhz

    reference clock frequency is 156.25Mhz

  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    9 months ago

    Hello Mel_tong,


    I did try to replicate the issue that you've mentioned but unfortunately I'm unable to see what you're observing at your end.

    Do you mind attaching the ip file that you've generated for debug purpose?


    Regards,

    Pavee


    • mel_tong's avatar
      mel_tong
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      9 months ago

      Hi Pavee,

      The zip is 10G IP. At the same time, there is also verilog for related parts.

      Regards,

      tong

  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    8 months ago

    Hello Mel_tong,


    Apologies' for delayed response.

    I'm able to see what you're referring to. May I know if what are the issue that you're observing?

    Because for now I haven't came across this has caused any issue so just wanted to check what is the observation at your end.


  • mel_tong's avatar
    mel_tong
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    8 months ago

    Hi Pavee,

    The first question: I am using the 10G phy project mentioned above and connecting it to another A10 FPGA's 10G Ethernet (this project ensures no issues). But I found on the STP of A10 that the XGMII signal at the receiving end is unstable, and the received data is not idle data 0x0707 but 0xfefe. So I want to know where went wrong.

    The second question is what is the latency of this phy? I have measured that the loopback delay from sending to receiving on the A10 chip's phy was about 130ns, but the PHY Agilex7 IP has already exceeded 300ns.

    Regards,

    tong

  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    7 months ago

    Hello Mel_tong,


    Good day to you.

    Have you tried with design example instead? And the latency for A10 and Agilex 7 is different. This 2 board has different latencies.


    Regards,

    Pavee


    • mel_tong's avatar
      mel_tong
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      7 months ago

      Hi Pavee,

      I used the example of E-Tile Ethernet IP for Intel Agilex 7 FPGA and it worked fine.
      But I couldn't find design example of E-Tile Transceiver Native PHY Intel Agilex 7 FPGA IP, so I made one according to the User Guide. The result is unstable.

      Can you provide an design example of E-Tile Transceiver Native PHY Intel Agilex 7 FPGA IP?And what is the latency of phy for Agilex 7? Do you have specific data?

      Regards,

      tong

  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    7 months ago

    Hello Mel_tong,


    Unfortunately we don't have an existing design example for E-Tile. No worries, I'm consulting with SME on Transceiver. I will let you know the update.


    Regards,

    Pavee


    • mel_tong's avatar
      mel_tong
      Icon for New Contributor rankNew Contributor
      6 months ago

      Hi Pavee,

      Is there any new progress in the affairs.

      Regards,

      tong